1. Field of the Invention
The present invention relates generally to semiconductor devices, and particularly to integrated circuit modules.
2. Technical Background
Integrated circuits are thin semiconductor chips that include a large number of semiconductor devices, i.e., transistors and resistors, disposed thereon. A typical semiconductor chip may have a surface area of approximately 10 mm2 to 600 mm2. Examples of integrated circuits include microprocessors, signal processors, and volatile and non-volatile memory devices.
Integrated circuits are fabricated by various steps that result in a circuit layer being disposed on a semiconductor wafer. The wafer may be comprised of silicon, gallium arsenide, or other such materials. For example, in some special applications, a substrate is formed by disposing silicon on sapphire. Photolithographic techniques are used to pattern the wafer. Repeated steps of deposition, patterning and etching are performed to build three-dimension circuit structures. Layers of resist, polysilicon, and other materials may be deposited on the substrate and later etched away to further define the circuit structure. After circuit elements such as transistors and resistors are constructed, these elements are interconnected by vias and lead lines. The interconnections may be formed, for example, by sputtering or electro-plating. The interconnection material may be aluminum, copper, or other metallic materials. Numerous integrated circuits are typically disposed on a single wafer. The wafer is subsequently cut into dies, or semiconductor chips.
Obviously, the speed at which signals propagate within an integrated circuit is a function of the surface area of the chip. In other words, the larger the separation distance between two circuit components, the slower the speed at which they are able to communicate. Accordingly, there is a need to reduce the length of the signal path to thereby increase the overall speed of the device.
In one approach that has been considered, the maximum signal distance is reduced by stacking integrated circuit chips in a three-dimensional structure. The length of the signal path is reduced because vertical distance between chip layers is generally smaller than the surface area of the chip itself. The cost of a two chip solution is also typically less for medium chip sizes due improved yields and process optimization for each chips content. However, one drawback to the stacked multi-chip approach relates to providing signal security. The chip layers may be separated to expose the chip interconnection points or the interconnections may be probed. Both allow the chip interconnection signals to be intercepted and monitored. What is needed is an integrated circuit module that prevents interconnection signals from being intercepted and monitored.